Parallel CRC scrambler and descrambler for 20b input words, VHDL model.
This scam&descam are for polynomial g(x)=x^9+x^4+1, but it can be easily changed.
Also this design is for 20b data bus, but it can be easily modified to accommodate any bus width.
http://rapidshare.com/users/4Z4U36
You'll need the password to open this folder, please contact me vie email if you need this.
cejkov.aleksandar@gmail.com
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1 comment:
There is an online tool at OutputLogic.com that generates Verilog or VHDL code for Scrambler with different data sizes and polynomials
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